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The IEEC values research as a means to create connections and to open future possibilities in the area of electronics packaging.

  

Pooled Research Projects

Every year, we provide what we call "seed-funding," to propel research opportunities in the direction of capacity building and problem-solving for faculty members in academia.

Skilled researchers partner with industry members to meet real-time project needs of companies. That is, whether you are a chemist, physicist, or mechanical engineer, to name a few, members of all fields carry expertise that is integral in catapulting the metrics of success for projects to reach new heights.

Below are the abstracts of the selected 2020-2021 Pooled Research Projects-a partnership between faculty and mentor companies.

2020-2021 Pooled Research Projects

• Fabrication of 3-dimensional integrated photonicdevices via femtosecond laser micromachining - Bonggu Shim

  In this proposed research, we will first investigate the optimal parameters for femtosecond laser
  micromachining of waveguides both in rigid and flexible glass substrates. Second, we will
  implement fully 3-dimensional laser micromachining setup which will be used for manufacturing
  integrated photonic devices. Third, we will utilize our 3-dimensional fabrication capability to
  manufacture spatial light multiplexers called photonic lanterns.

• Modeling Temperature-Dependent Properties ofSolder Interfaces - Manuel Smeu
  Building on our recent computational work investigating the temperature-dependent elastic properties of
  materials, we will now extend our efforts towards interfaces of solder assemblies. We will use a
  combination of density functional theory (DFT) and ab initio molecular dynamics (AIMD) to investigate
  the elastic moduli, Poisson’s and Pugh ratios of solder interfaces as a function of temperature. With these
  data we will also analyse the hardness, Debye temperature, elastic wave velocity, and coefficient of thermal
  conductivity as a function of temperature. In addition, we will also use the volume-energy relationship,
  coupled with the Vinet equation of state to calculate the temperature-dependent coefficient of thermal
  expansion of these materials. We are particularly interested in the Sn-Bi solder joint as well as other lowtemperature solders. With the combination of these computational
  efforts we aim to identifying potential weak spots and failure
  mechanisms in these junctions.
• Inorganic Composite Phase Change Materials forPassive Thermal Management - Hao Liu
  This proposal aims to develop high-energy-density inorganic salt hydrate/carbon foam composite
  phase change materials for passive thermal cooling in electronics. This work is expected to yield
  a form-stable carbon foam/Ba(OH)2·8H2O composite phase change material with four times as
  much thermal energy storage density as the existing paraffin wax. The proposed project will
  optimize the critical wetting property between carbon foam and Ba(OH)2·8H2O through a systemic
  investigation of strategies for hydrophilic modification of carbon foam.
• Multi-Material Additive Manufacturing of  Non-Planar Flexible Substrates with ConformallyConductive Traces for Integrated Electronics - Fuda Ning
  Current additive manufacturing (AM) processes lack the ability to construct integrated
  electronics with non-planar, conformally patterned features during a single build. In this
  proposed research, we present a novel multi-axis multi-head AM approach for one-step
  fabrication of non-planar flexible electronics. The objective is to advance fundamental
  understanding of this innovative multi-material printing of electronics while integrating direct
  ink writing, fused filament fabrication, and machining processes. The underlying materialprocess-structure-performance connection will be deciphered through numerical and
  experimental investigations. The curve-shaped PET substrate with tailored surface roughness
  will be created with the subsequent depositions of Cu and/or Ag traces and their geometrical,
  structural, and electrical effectiveness will be assessed. In addition, the interfacial adhesion
  and failure mechanisms will be elucidated by finite element analysis and mechanical testing
  including peeling/shear tests and tension/bending fatigue tests. Finally, we will fabricate 3D
  integrated circuits by multi-layer deposition to offer the embedded solutions that maximize
  the functional capability for 3D integration/packaging.
• Cyber-Physical and Intelligent Edge ComputingPlatform for Smart Connected Manufacturing” - Wenfeng Zhao
  The aim of this proposal is to develop KcASE (Figure 1, blue), a cyber-physical and intelligent
  edge computing hardware platform for connected and intelligent industrial 4.0 paradigm. In
  particular, we consider one use case for the state-of-the-art SMT (surface mount technologies)
  inline manufacturing (Figure 1, gray) and real-time quality inspection (Figure 1, green). We plan
  to accomplish two specific tasks to achieve the connectivity and intelligence extension to the entire
  product line. First, we will develop a communication module with versatile interfaces (COM,
  Ethernet, etc.,) that can be used for bidirectional communication among KcASE, 3
  rd
  -party
  equipment and Koh Young Inspection machines. Second, we will integrate the communication
  module with the latest embedded AI computing hardware and study efficient, distributed edgenode inference. Upon the success of this project, we envision that KcASE can pave the way for
  comprehensive AI-driven, closed-loop process optimization strategies in SMT inline production.
  KcASE can also be regarded as a feasibility exploration effort toward a potential future product,
  i.e., an edge extension to KBOX for cost-effective industrial 4.0 deployment solutions.
• Automated integration with micro/nanowirebasedfine-pitch interconnects for 3D packaging - Kaiyan Yu
  This project aims to create novel micro or nanowire-based fine-pitch interconnects for 3D
  packaging using precisely controlled micro or nanowires. An automated, precise 3D manipulation
  scheme is proposed to assemble multiple micro and nanowires in fluid suspension under electrical
  field. A solution-based approach is designed fabricating interconnects using vertically aligned and
  horizontally patterned micro or nanowires. This project addresses important challenges regarding
  the precise and scalable assembly for high density interconnects in 3D packaging.
• The Electromigration Behavior of Pb Free Solder Jointscontaining Bi: High Melt - Low Melt SolderInterconnect Structures for SMT Applications - Eric Cotts
  We will study the materials science of SAC/BiSn solder joints (e.g., SAC305/Bi42Sn, Fig. 1a)
  and on such mixed assemblies when both board
  and component are bumped (Fig. 1b), which
  promise to provide lower temperature
  assembly for a wide range of conditions. The
  eutectic Bi42Sn solder alloy enables process
  temperatures as low as 150o
  C (Fig. 2) and is
  widely available in paste form (the Bi42Sn1Ag
  is a popular variant intended to improve
  interfacial toughness in drop shock
  loading). We propose to examine the
  properties of mixed solder alloy joints with
  combinations of SAC305 or SAC405 solder
  balls, and Bi42Sn or Bi42Sn1Ag solder paste
  (Fig.1). Key parameters will include the
  thickness (volume) of the near eutectic BiSn paste, the peak reflow temperature and reflow time, and
  fabrication parameters (in particular, variation of geometry from that of Fig. 1a to that of Fig. 1b).
  We will examine microstructures of final joints, determining grain sizes
  and orientations, as well as composition throughout the joints (including
  Bi concentration). Mechanical characterization will include hardness and
  shear characteristics of individual and mixed assembly solder joints.
  Furthermore, characterizations of the current density limits of such SnBi mixed assemblies will be conducted over a range of current densities,
  temperatures, and geometries, with focus on the newer geometry
  illustrated in Fig. 1b. Fabrication of such samples will be by conventional
  means. Building an understanding of the materials science of these new
  solder joints will provide for reliable product design capability.
• “Understanding and Preventing Voiding in Small Ni-SnJoints Through Design and Process Control - Nikolay Dimitrov
  This proposal addresses defects in Sn or solder based joints at scales ranging from BGA to ultra-fine flip chip
  assemblies.
  Microjoints in 2.5/3D assembly are commonly formed by small Sn or solder caps between opposing Cu or Ni
  surfaces. Ongoing work funded by the IEEC is leading to a systematic characterization of the strongly
  enhanced risk of Kirkendall voiding within the intermetallic bonds in microjoints on Cu surfaces. This
  problem is found to be associated with the quality of the electroplated Cu and guidelines will be offered as to
  how to minimize the risk.
  An alternative is the use of Ni or Ni/Au coated pillars or pads. Very small Sn thicknesses and repeated
  reflows, like in stacking of chips, and/or subsequent exposure to elevated temperatures may however lead the
  intermetallic layers from opposing surfaces to meet. Alternatively, this may be done on purpose to provide
  for solid support in repeated thermocompression bonding when stacking die or to eliminate concerns with
  respect to electromigration and thermomigration through unfortunately oriented Sn grains. In either case,
  collision between the highly irregular intermetallic surfaces tends to lead to the entrapment of a row of Sn
  ‘pockets’ which are finally drained of Sn, leaving severe voiding.
  Another concern with slightly larger Ni based joints is the formation of large voids between the Ni3Sn4
  intermetallic surface and the solder. Several research groups suggest that the formation of such voids is
  inevitable once the intermetallic thickness starts to exceed 5µm.
  It is proposed to characterize the effects of interactions between design, electroplating process chemistry and
  parameters, assembly process parameters, and subsequent thermomechanical history on either of these
  phenomena. The goal is to establish practical guidelines for how to minimize or, preferably, entirely
  eliminate the voiding.
• Machine learning application for controlling SMTreflow oven - Jia Deng & Sangwon Yoon
  Research Problem: Thermal interface materials are a bottleneck to heat flow, and limit performance as performance increases.
  Research Objective: The goal is to develop an alternative solution for thermal interface materials by metal additive manufacturing which provides lower thermal resistance and enables packages with heat fluxes up to ~1,000 W/cm2.
  Technical Approach: We will develop the process parameters to additively fabricate Cu and/or AlSi10Mg structures on a die (CPU, GPU etc.) using Sn3Ag4Ti interlayer alloy by selective laser melting. The structures can be micro-channels, heat pipes or vapor chamber evaporators. Furthermore, we will look at the interface microstructure and composition of Si-interlayer alloy and Cu and/or AlSi10Mg-interlayer alloy by scanning electron microscopy (SE2, EDS, BEI) and transmission electron microscopy (SAED, BF, DF, EDS). Vibratory polishing, focused ion beam (FIB) and Argon beam ion milling will be used along conventional polishing techniques for sample preparation. We will evaluate the strength of the interfacial bonding by mechanical testing such as ball shear tests and finite element analysis simulations. Thermal properties of the fabricated heat sink structures will be experimentally measured using Frequency-Domain Thermoreflectance (FDTR) analysis across the interface. Finally, the performance of the additively fabricated heat sink will be evaluated experimentally and numerically in single phase and two-phase scenarios.
  Anticipated Outcome: We will develop a process to additively fabricate thermal management devices onto the chip without using conventional thermal management solutions which lead to lower thermal resistance in the package.
  Industry Impact: Current thermal interface materials will not be able to keep up with Moore’s Law, whereas our alternative solution will enable 10X increase in heat fluxes (~1,000 W/cm2). By our calculations, chips can run 10-20 °C cooler under heat fluxes of 100 W/cm2 in current microprocessors.
• Nano-crystalline Planar Magnetic Components forhigh power density solid state transformer in AC-DC Power Converters used for Integration of Li-ionbatteries to AC Systems - Pritam Das & Scott Schiffres
  Current power conversion is only 90% efficient, primarily due to losses in the magnetic components. This power
  conversion is increasingly important for the power grid, vehicles, aerospace and defense. This proposal seeks a 3D
  printed enhanced magnetic component that can reduce transformer losses, while maintaining a compact design. Our
  goal is to develop technologies that will create a transformer with an efficiency of greater than 95%, a 50% reduction
  in losses compared to today’s standards. 3D printed cores with varying processing conditions will be manufactured
  and the effect of the processing on microstructure and magnetic properties will be investigated. This proposal will
  be leveraged into larger future proposals.

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