ºÚÁÏÊÓƵ

The IEEC values research as a means to create connections and to open future possibilities in the area of electronics packaging.

  

Pooled Research Projects

Every year, we provide what we call "seed-funding," to propel research opportunities in the direction of capacity building and problem-solving for faculty members in academia.

Skilled researchers partner with industry members to meet real-time project needs of companies. That is, whether you are a chemist, physicist, or mechanical engineer, to name a few, members of all fields carry expertise that is integral in catapulting the metrics of success for projects to reach new heights.

Below are the abstracts of the selected 2024-2025 Pooled Research Projects-a partnership between faculty and mentor companies.

2024-2025 Pooled Research Projects

• Soldering Below 150C – Superior Reliability? - Peter Borgesen

  There is a growing interest in assembly with peak reflow temperatures below 200C, but approaches currently being considered are not applicable to general SMT assembly and/or they lead to fatigue properties that are inferior to those of the most common solder alloy today, SnAg3Cu0.5 (SAC305).

  We have identified a couple of alloys that allow for peak reflow temperatures near or below 150C, leading to solder joints that performed better than SAC305 in room temperature cycling. With melting points below 130C these alloys may however well be less competitive at higher temperatures and perhaps also in thermal cycling. Assessments of this will require characterization of deformation and damage properties vs temperature together with a mechanistic understanding. Notably, accelerated thermal cycling tests should not exceed actual operating temperatures of concern to not unduly favor SAC305 in a comparison.

  It is proposed to characterize the properties and establish the understanding required, including effects of design and process parameters. This will be concluded by testing of assemblies in the most suitable accelerated tests.

• SiC MOSFET Module Design for Ultra Low Inductance and Improved Thermal Conductivity for High Switching Frequency, High Voltage and High Current Applications - Pritam Das
  This proposal researches on design of SiC MOSFET power modules with ultra-low loop inductance, high thermal conductivity, ease of manufacturing for packaging multiple series connected Silicon Carbide (SiC) Power MOSFET for switching at frequencies above 100 kHz with high switching speed of 20~30ns from high voltage above 1 kV and high currents of several 10s of amperes. SiC MOSFETs are capable of switching at high speeds to reduce switching losses and increase switching frequency of power converters to reduce the size and weight of their filtering components and potentially increase power density of the overall converter.
• Oxidation and Corrosion Induced Deterioration of Fatigue Resistance of Sintered Nano-Cu and Nano-Ag Bonds and Interconnects - Nikolay Dimitrov, Peter Borgesen

  An ongoing IEEC project funded at a level supporting a student for one semester is starting to yield results, pointing to a need for a larger systematic study of the effects of even mild oxidation on the fatigue resistance of sintered structures.

  There is a growing interest in the use of sintered nano-Cu and nano-Ag, as both self-supporting joints and bonds as well as lines on various substrates. These structures are invariably nano-porous, but because of the ductility of the narrow links (ligaments) between the particles, especially after mild cyclic loading (‘work softening’), the structures are usually not as brittle as one might have feared. However, this may change after a level of exposure to oxidation and/or corrosion that would certainly not be a problem for non-porous structures.

  In fact, while the electrical properties of nano-porous structures of course tend to be much more sensitive to corrosion than those of non-porous ones, the deformation and damage properties are even more so. Long before corrosion becomes electrically detectable, it may strongly reduce the ductility and fatigue resistance of the porous structures. In the case of Ag, at least, we find this to depend on the specific corrosion mechanism, and thus on the environment. In fact, preliminary results suggest that an oxidative mechanism that converts the structures into a soluble ionic form may quickly remove oxides formed during sintering of the Ag in air, initially leading to an improved fatigue resistance. However, work is ongoing to assess the effects of another mechanism and longer exposure times.

  The present proposal focuses instead predominantly on the effects on sintered nano-Cu structures. Even relatively mild oxidation was found to embrittle such structures, strongly reducing their fatigue resistance. It is proposed to complete current studies on sintered nano-Ag but to emphasize effects of oxidation and corrosion on sintered nano-Cu structures. The focus of these studies will be on the anticipated faster degradation with the corrosion progression. The effects of high angle/curvature grain boundaries and the tendency to have enhanced mechanical deformation in said structural features will be subject of quantitative interest. Another angle of looking into this relationship will be the reversed scenario when cyclic loading induced dislocation structures tend to further enhance rates of corrosion there.

• μ+Net: Automating AdderNet Deployment and Acceleration on Microcontroller-based Platforms for Sustainable and Ubiquitous Edge AI - Wenfeng Zhao

  This project aims to develop μ+Net (micro-AdderNet), a novel edge AI (artificial intelligence) compiler framework for the optimal and automated deployment of the emerging multiplication-less deep learning model AdderNet, onto resource-constrained COTS MCUs (commercially-off-the-shelf micro-controllers) based sensor platforms. Built upon a hardware-efficient SAD (sum-of-absolute difference) kernel, we will demonstrate that AdderNet-based AI models can achieve an inference runtime reduction by more than 100% and significant power savings with uncompromised model accuracy when compared to the prevailing CNN counterparts. We will develop a comprehensive set of tools, including model parsing and quantization, dataflow optimization, and parallel computing software generation, towards automated AdderNet deployment on MCUs.

  We envision that the success of this project will offer a powerful edge AI solution that can be readily deployed in COTS MCUs, and enable a great span of applications of interest to IEEC member companies like GE (AI-based Inspection & Smart Sensors) and BAE (SWAP-C & Sensors in aircrafts and vehicles), as well as ADI and AMD that have already invested heavily in AI-MCU and edge-AI domains (MAX78000/MAX78002, AMD Kria Adaptive SOM).

• AI-Driven Inverse Design for Tailoring the Multidirectional Mechanical Properties of Stochastic Cellular Materials - Jalil Razavi
  Our objective is to establish and validate an innovative AI-driven framework for inversely tailoring the multidirectional mechanical properties of stochastic cellular structures. To achieve this goal, we will design and test stochastic cellular materials with predefined simultaneous and unique mechanical properties in various loading directions using artificial intelligence (AI) techniques. The designed structures will undergo additive manufacturing and mechanical testing to validate the performance of the proposed framework by measuring and comparing the acquired multidirectional mechanical properties with the requested properties.
• Copper-based Nanoalloy Inks for Ambient- and High-Temperature Device Applications - Chuan-Jian Zhong

  For printed electronics and sensors, not only the ambient-temperature sintering capability is critical for low-temperature required microfabrication, but also the high-temperature device performance is essential for many applications. Fundamental questions for such temperature-dependent microfabrication and applications include controllability over nanoink composition and formulation in scalable production, electrical conductivity and stability, densification and porosity at microscopic level, device operation at elevated temperature and bending, and chemical stability in terms of oxidation, corrosion resistances.

  The proposed project will focus on addressing these technical challenges by investigating scalable synthesis and formulation of copper-based nanoalloy inks (CuAg and CuAu) and microfabrication of printed sensors on fibrous cellulose paper and flexible fiber ceramic paper substrates, which feature different requirements in terms of sintering and application temperatures. Key deliverables include fundamental knowledge and technical capabilities for scale-up synthesis and formulation of copper-based nanoalloy inks, and microfabrication of printed devices for ambient- and high-temperature applications.

• Smart Solutions for the Conformal Coating Progress: Optimizing Processes Parameters with AI-based Defects Detections - Sangwon Yoon, Daehan Won
  The conformal coating process for PCBs requires understanding the correlation between atomization process parameters, environmental conditions, and coating quality. This project aims to study three main areas: the diagnosis of defects like bubbles, sharp edge coverage, cracking, de wetting, and delamination. The development of an AI-based bubble detection algorithm to identify and analyze defects through pattern recognition and the optimization of the coating process by correlating specific processes and material parameters with coating quality. Expected outcomes include a defect diagnosis module that provides a holistic view of the atomization conformal coating process, an advanced bubble detection algorithm for precise defect identification, and an optimization module for the atomization process that incorporates mathematical programming and physical knowledge to facilitate smart, interpretable results and optimal parameter settings without the need for extensive manual adjustments.
• Simulating The Efficiency and Thermal Expansion of a Thermoelectric-Gated Transistor from First Principles - Manuel Smeu
  Durability of chips, circuits, and board-level components subject to thermal stress and cycling is a significant limiting factor in modern electronics. Efforts to utilize waste heat from chip architectures can aid in thermal regulation by allowing lower circuit footprint options for temperature sensing and cooling apparatuses. A field effect transistor (FET) with a thermoelectric gate electrode in particular offers exciting prospects, particularly in application to temperature-dependent circuit processes. We will use density functional theory (DFT) as well as a non-equilibrium Green’s function formulation of DFT (NEGF-DFT) to model the operation and efficiency of thermoelectric-gated transistors from first principles. We will characterize the efficiency through electrical conductivity, Seebeck coefficient, and thermal conductivity calculations. In addition, to ensure that the thermoelectric-gated transistor we simulate can withstand thermal cycling, we will calculate the coefficients of thermal expansion (CTE) for all components of the transistor design and attempt to match these CTE values to existing chip- and board-level electronic component materials. Through this computational investigation, we aim to demonstrate a thermoelectric transistor design that enables small and simple cooling solutions dependent on chip temperature to take effect on the circuit- and board-level.
• Modeling Current Flow through Interconnects with Thermal Atomic Motion and Alternating Bias - Manuel Smeu
  Building on our recent work modeling current flow through copper with rough surfaces and barrier layers, we will now explore how the effects of ambient temperature in normal to extreme temperature environments affects current flow across the interconnect via thermally-induced motion of atoms in the model interconnect. We will then introduce oxygen (O2) molecules to simulate how the presence of environmental oxygen alters current flow across the interconnect. This will allow us to identify how previously identified behaviors in our work, such as the exceptionally conductive nature of an Ag barrier layer, are affected by extreme temperature environments and oxygenated atmospheres. We will then investigate how different barrier layer compositions facilitate or impede electron flow across the interconnect when subject to an alternating current (AC) bias. Through these efforts, we aim identify key tradeoffs that our industrial partners can leverage to produce higher-quality devices.

Join our membership to have access to the latest reports and findings of our research projects.